0824 4233176
PROJECT4U
0824 4233176
PROJECT4U
| 1 | |
2016 | LOW POWER |
| 2 | |
2016 | LOW POWER |
| 3 | 2016 | LOW POWER | |
| 4 | 2016 | LOW POWER | |
| 5 | 2016 | LOW POWER | |
| 6 | Low-Power FPGA Design Using Memoization-Based Approximate Computing | 2016 | LOW POWER |
| 7 | Low-Power Split-Radix FFT Processors Using Radix-2 Butterfly Units | 2016 | LOW POWER |
| 8 | A High-Speed FPGA Implementation of an RSD-Based ECC Processor | 2016 | HIGH SPEED DATA TRANSMISSION |
| 9 | High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels | 2016 | HIGH SPEED DATA TRANSMISSION |
| 10 | A 0.52/1 V Fast Lock-in ADPLL for Supporting Dynamic Voltage and Frequency Scaling | 2016 | HIGH SPEED DATA TRANSMISSION |
| 11 | Code Compression for Embedded Systems Using Separated Dictionaries | 2016 | HIGH SPEED DATA TRANSMISSION |
| 12 | A Dynamically Reconfigurable Multi-ASIP Architecture for Multi- standard and Multimode Turbo Decoding | 2016 | HIGH SPEED DATA TRANSMISSION |
| 13 | Design and Implementation of High-Speed All-Pass Transformation-Based Variable Digital Filters by Breaking the Dependence of Operating Frequency on Filter Order | 2016 | HIGH SPEED DATA TRANSMISSION |
| 14 | A Mixed-Decimation MDF Architecture for Radix-2K Parallel FFT | 2016 | AREA EFFICIENT/ TIMING & DELAY REDUCTION |
| 15 | Algorithm and Architecture of Configurable Joint Detection and Decoding for MIMO Wireless Communications With Convolution Codes | 2016 | AREA EFFICIENT/ TIMING & DELAY REDUCTION |
| 16 | One-Cycle Correction of Timing Errors in Pipelines With Standard Clocked Elements | 2016 | AREA EFFICIENT/ TIMING & DELAY REDUCTION |
| 17 | Hardware and Energy-Efficient Stochastic LU Decomposition Scheme for MIMO Receivers | 2016 | AREA EFFICIENT/ TIMING & DELAY REDUCTION |
| 18 | Hybrid LUT/Multiplexer FPGA Logic Architectures | 2016 | AREA EFFICIENT/TIMING & DELAY REDUCTION |
| 19 | A 520k (18 900, 17 010) Array Dispersion LDPC Decoder Architectures for NAND-Flash Memory | 2016 | AREA EFFICIENT/ TIMING & DELAY REDUCTION |
| 20 | Implementing Minimum-Energy-Point Systems With Adaptive Logic | 2016 | AREA EFFICIENT/ TIMING & DELAY REDUCTION |
| 21 | High-Performance Pipelined Architecture of Elliptic Curve Scalar Multiplication Over GF(2m) | 2016 | AREA EFFICIENT/ TIMING & DELAY REDUCTION |
| 22 | High-Performance NB-LDPC Decoder With Reduction of Message Exchange | 2016 | AREA EFFICIENT/ TIMING & DELAY REDUCTION |
| 23 | LUT Optimization for Distributed Arithmetic-Based Block Least Mean Square Adaptive Filter | 2016 | AREA EFFICIENT/ TIMING & DELAY REDUCTION |
| 24 | Graph-Based Transistor Network Generation Method for Supergate Design | 2016 | AREA EFFICIENT/ TIMING & DELAY REDUCTION |
| 25 | Flexible DSP Accelerator Architecture Exploiting Carry-Save Arithmetic | 2016 | AREA EFFICIENT/ TIMING & DELAY REDUCTION |
| 26 | A Cellular Network Architecture With Polynomial Weight Functions | 2016 | AREA EFFICIENT/ TIMING & DELAY REDUCTION |
| 27 | A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications | 2016 | AREA EFFICIENT/ TIMING & DELAY REDUCTION |
| 28 | Fault Tolerant Parallel FFTs Using Error Correction Codes and Parseval Checks | 2016 | AREA EFFICIENT/ TIMING & DELAY REDUCTION |
| 29 | Exploiting Intracell Bit-Error Characteristics to Improve Min-Sum LDPC Decoding for MLC NAND Flash-Based Storage in Mobile Device | 2016 | AREA EFFICIENT/ TIMING & DELAY REDUCTION |
| 30 | Unequal-Error-Protection Error Correction Codes for the Embedded Memories in Digital Signal Processors | 2016 | AREA EFFICIENT/ TIMING & DELAY REDUCTION |
| 31 | A High Throughput List Decoder Architecture for Polar Codes | 2016 | AREA EFFICIENT/ TIMING & DELAY REDUCTION |
| 32 | A Normal I/O Order Radix-2 FFT Architecture to Process Twin Data Streams for MIMO | 2016 | AREA EFFICIENT/ TIMING & DELAY REDUCTION |
| 33 | Design and FPGA Implementation of a Reconfigurable 1024- Channel Channelization Architecture for SDR Application | 2016 | AREA EFFICIENT/ TIMING & DELAY REDUCTION |
| 34 | Input-Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding | 2016 | Audio, Image and Video Processing |
| 35 | A Configurable Parallel Hardware Architecture for Efficient Integral Histogram Image Computing | 2016 | Audio, Image and Video Processing |
| 36 | A New Binary-Halved Clustering Method and ERT Processor for ASSR System | 2016 | Audio, Image and Video Processing |
| 37 | The VLSI Architecture of a Highly Efficient De-blocking Filter for HEVC Systems | 2016 | Audio, Image and Video Processing |
| 38 | Low-Power System for Detection of Symptomatic Patterns in Audio Biological Signals | 2016 | Audio, Image and Video Processing |
| 39 | In-Field Test for Permanent Faults in FIFO Buffers of NoC Routers | 2016 | NETWORKING |
| 40 | Source Code Error Detection in High-Level Synthesis Functional Verification | 2016 | Verification |
| 41 | A Single-Ended With Dynamic Feedback Control 8T Subthreshold SRAM Cell | 2016 | TANNER /MICROWIND – (AREA EFFICEINT) |
| 42 | OTA-Based Logarithmic Circuit for Arbitrary Input Signal and Its Application | 2016 | TANNER /MICROWIND – (AREA EFFICEINT) |
| 43 | A Robust Energy/Area-Efficient Forwarded-Clock Receiver With All-Digital Clock and Data Recovery in 28-nm CMOS for High- Density Interconnects | 2016 | TANNER /MICROWIND – (AREA EFFICEINT) |
| 44 | Full-Swing Local Bitline SRAM Architecture Based on the 22-nm FinFET Technology for Low-Voltage Operation | 2016 | TANNER /MICROWIND – (AREA EFFICEINT) |
| 45 | 4A 0.1–3.5-GHz Duty-Cycle Measurement and Correction Technique in 130-nm CMOS | 2016 | TANNER /MICROWIND – (AREA EFFICEINT) |
| 46 | A Low-Power Robust Easily Cascaded PentaMTJ-Based Combinational and Sequential Circuits | 2016 | TANNER /MICROWIND – (LOW POWER) |
| 47 | Low-Power Variation-Tolerant Nonvolatile Lookup Table Design | 2016 | TANNER /MICROWIND – (LOW POWER) |
| 48 | Low-Energy Power-ON-Reset Circuit for Dual Supply SRAM | 2016 | TANNER /MICROWIND – (LOW POWER) |
| 49 | Frequency-Boost Jitter Reduction for Voltage-Controlled Ring Oscillators | 2016 | TANNER /MICROWIND – (LOW POWER) |
| 50 | High-Speed, Low-Power, and Highly Reliable Frequency Multiplier for DLL-Based Clock Generator | 2016 | TANNER /MICROWIND – (LOW POWER) |
